As semiconductor devices have become highly integrated, approaches have been developed for decreasing a size of a unit element by reducing a length of a gate electrode, a thickness of a gate insulation layer, and a width of an isolation layer. However, among scaling factors in a semiconductor device, controlling the length of the gate electrode is difficult and, therefore, is expensive to perform. In addition, a short channel effect is known as a characteristic that is difficult to be controlled in a transistor manufacturing process.
To resolve such problems, U.S. Pat. Nos. 6,583,017 and 5,571,738 disclose a method for forming a lightly doped drain (hereinafter referred to as “LDD”) region by an ion implantation process.
However, an improved process is still required that is capable of easily controlling the length of the gate electrode and suppressing the short channel effect.